In most signal "timing diagrams" (like the one below) the signals do not change from low to high, or from high to low, abruptly. in other words there is a very short time (relative to the clock cycle and a very very tiny amount) when the signal "transits" between the two levels. explain what the meaning of this "transient" state is, and how it is explained. signal timing diagram example

Explanation:

This transient state occurs due to the fact that the signal change from low to high and high to low doesn't occur intermediately but in a very small time, in relation to the signal time itself.

At transistor level there are parasitic (undesired) capacitances and resistances, formed due to the layout configuration of conductor and dielectrics. As consequence a RC circuit is formed, thus making a propagation delay.

This delay must be characterized for each circuit, and specified as tpHL (transition time from High to Low) and tpLH (transition time from Low to High)

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