Following specifications, what is the size of l2 cache that achieves the lowest energy for the pmd (core, l1, l2, memory) for that given task? a. the core frequency is 1 ghz, and the l1 has an mpki of 100. b. a 256 kb l2 has a latency of 10 cycles, an mpki of 20, a background power of 0.2 w, and each l2 access consumes 0.5 nj. c. a 1 mb l2 has a latency of 20 cycles, an mpki of 10, a background power of 0.8 w, and each l2 access consumes 0.7 nj. d. the memory system has an average latency of 100 cycles, a background power of 0.5 w, and each memory access consumes 35 nj.

solution:

this situation is called an ip conflict.

data from a server is sent in small bits called packets. in an ip conflict, some packets will end up in one computer while some other packets will end up in another computer.

so…overall none of the computers get the data as the original message or picture being sent by the server cannot be retrieved with only half the packets. so it will show up as an error.

thus the final answer is d.

hey! im not 100 percent sure but im pretty sure that what you want to do is not possible : (

explanation:

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