Design a 4-bit register with both shift and parallel load features. the inputs of

the register include a 2-bit control code x y, a 4-bit input value i3 i2 i1 i0, and a clock signal. the

outputs of the register are the 4 bits q3 q2 q1 q0 corresponding to the value stored in the

register. you are allowed to use any number of d flip-flops, muxes of any size, decoders and

encoders of any sizes, and gates, or gates, and not gates. (notice that you do not need all of

them.) the operations of the register is defined below:

x y operation

0 0 hold the current value stored (i. e., q3 q2 q1 q0 are not changed)

0 1 shift right (i. e., new q3=i3, new q2=q3, new q1=q2, new q0=q1)

1 0 shift left (i. e., new q3=q2, new q2=q1, new q1=q0, new q0=i0)

1 1 load new date (i. e., new q3=i3, new q2=i2, new q1=i1, new q0=i0)