Computers and Technology, 16.11.2019 01:31 lasardia

For this problem, assume that all branches are perfectly predicted, eliminating all control hazards, and that no delay slots are used. if we change load/store instructions to use a register without an offset as the address, these instructions no longer need to use the alu. as a result, mem and ex can be overlapped and the pipeline has only 4 stages. change the code to accommodate this changed isa. assuming this change does not affect clock cycle time, what speedup is achieved in this instruction sequence?

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