5.2 caches are important to providing a high-performance memory hierarchy to processors. below is a list of 32-bit memory address references, given as word addresses.

3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253

5.2.3 you are asked to optimize a cache design for the given references. there are three direct-mapped cache designs possible, all with a total of 8 words of data: c1 has 1-word blocks, c2 has 2-word blocks, and c3 has 4-word blocks. in terms of miss rate, which cache design is the best? if the miss stall time is 25 cycles, and c1 has an access time of 2 cycles, c2 takes 3 cycles, and c3 takes 5 cycles, which is the best cache design?