Design a 4-bit register with 2 control inputs s1 and s0, 4 data inputs i3, i2, i1, and i0, and 4 data outputs q3, q2, q1, and q0. when s1s0=00, the register maintains its value. when s1s0=01, the register loads i3..i0. when s1s0=10, the register clears itself to . when s1s0=11, the register complements itself, so, for example would become , and 1010 would become 0101.