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The pipelined MIPS processor is running the following program. Which registers are being written, and which are being read on the fifth cycle?
a. addi $s1, $s2, 5
b. sub $t0, $t1, $t2
c. lw $t3, 15($s1)
d. sw $t5, 72($t0)
e. or $t2, $s4, $s5

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