We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of time. The original machine had a clock cycle time of 7 ns. After the stages were split, the measured times were IF, 1 ns; ID, 1.5 ns; EX, 1 ns; MEM, 2 ns; and WB, 1.5 ns. The pipeline register delay is 0.1 ns.

a. What is the clock cycle time of the 5-stage pipelined machine?
b. If there is a stall every 4 instructions, what is the CPI of the new ?machine?
c. What is the speedup of the pipelined machine over the single- cycle machine?
d. If the pipelined machine had an infinite number of stages, what would its speedup be over the single-cycle machine?

a) First, we need to determine the pipeline stage amounting to the maximum time. In the given case, the maximum time required is 2ns for MEM. In addition, the pipeline register delay=0.1 ns.

Clock cycled time of the pipelined machine= max time+delay

=2ns+0.1 ns

=2.1 ns

b) For any processor, ideal CPI=1. However, since there is a stall after every four instructions, the effective CPI of the new machine is specified by:

c) The speedup of pipelined machine over the single-cycle machine=avg time per instruction of single cycle/avg time per instruction of pipelined.

Single cycle processor:

CPI=1

Clock period=7 ns

Pipelined processor:

Clock period=2.1 ns

CPI=1.25

Therefore, speedup=

=7/2.625

= 2.67

d) As the number of stages approach infinity, the speedup=k where k is the number of stages in the machine.