Computers and Technology, 31.03.2020 00:56 shiba8667
1. Defines and uses an interface block to connect to the test program and the DUT. The interface block should also contain a clocking block and modport statements for defining signal direction to the testbench and to the DUT. 2. Generates the clock signal 3. Applies reset at the beginning 4. Checks the success of the reset operation and displays a success/fail message 5. Makes use of a class for defining random variables and a dynamic array to hold the random values. 6. Constraints the generated random values such that the number of generated random values (i. e. size of dynamic array) is less than 500 and their sum will be greater than 16'h 7. Applies the generated random values to the design input (in), one at every clock cycle 8. Checks the correctness of the design output (sum) at every clock cycle while applying inputs, and reports if there is a mismatch between the output of the design and the expected output.
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1. Defines and uses an interface block to connect to the test program and the DUT. The interface blo...
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