Computers and Technology, 09.04.2020 19:40 thesavagefatima

Consider a memory system with a two-level hierarchy with a cache M1 and main memory M2. The size of the main memory, M2 is 256 bytes with block size of 16 bytes. The size of the cache, M1 is 64 bytes with the same block size of 16 bytes. The word length is 4 bytes, implying 4 words per block. A certain trace program generates the following sequence of word addresses,

0,8,16,1,24,21,20,3,32,61,31,19,16, 60,28,21,8,11,19,22,28,42,55,58,59< br />
Note, every time a new block is accessed by the cache, up to 4 words are received implying that if block 0 is accessed from the main memory then 0,1,2,3 words are obtained, if block 1 is accessed from the main memory, words 4,5,6,7 are obtained, if block 2 is accessed from the main memory words 8,9,10,11 are obtained and so on. The addresses given above are word addresses, not memory block addresses. Assume that the access time is 2 clocks from the cache (M1) and 50 clocks from main memory (M2), the transfer rate is 4 bytes per clock and that 25% of the transfers are dirty. The base CPI of a perfect memory system is 1.75.

(a) Consider a fully associative cache with LRU replacement policy. Determine the hit ratio. What is the average memory access time?

(b) Consider a direct mapped cache. Determine the hit ratio. What is the average memory access time?

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