Implement a 4-to-1 multiplexer in SystemVerilog called mux4to1.sv. using a case statement. Use three instances of this code as sub-modules to implement an 8-to-1 multiplexer named mux8to1.sv OR use two instances of this code as sub-modules plus an if-else statement to implement an 8-to-1 multiplexer named mux8to1.sv. Perform a simulation of the 8-to-1 mux in ModelSim and use the Wave diagram to demonstrate that it works as expected. Turn in a Word or PDF document with copies of both SystemVerilog files and a screen capture of the ModelSim waveform.