Given the following sequences of word addresses, in decimal, 1, 4, 2, 7, 25, 4, 27, 3, 5, 24, 19, 18, 57, 1, 27, 3, 11 (no modification needed, just convert to binary 1 is 000001, 56 is 111000, etc, these are memory addresses) 1) Simulate an 8 word cache with one word per block, direct mapped. a) For each address, list the six bit binary and indicate H for hit, M for miss. b) Draw the cache showing cache binary address and cache contents after all addresses have been processed. Use (1) for the contents of memory address 1, (4) for the contents of memory address 4, etc. Show valid bit and tag.