This assignment will help you understand the behavior of cache memories and the impact that cache memories have on performance. You may work individually, or as a group consisting of up to 4 individuals. The assignment consists of two parts. In the first part, you will deduce the cache parameters such as block size, number of sets, number of ways, and hit time for a two-level cache simulator. In the second part, you will optimize a matrix multiply function to minimize the average memory read time. You will turn in not only your C code for the cache-optimized matrix multiply, but also a short report documen

Cache memory is a set of memory locations that serves fast access applications. Cache memory can store both data and instructions. Both data cache and instructions cache are increasing performance of a processor.

Structurally cache memory consist of sub-banks. Each sub-bank of cache consists of ways, that are made of lines. Lines consist of collections of consecutive bites.

Ways and lines are forming locations where data and instructions are stored in cache.

Processor uses tag arrays to find information in cache. Every line in cache has tag arrays. Tag array indicates if researched information exists in cache. Another thing processor check is validity bit to see if the cache line is valid or invalid. If it is valid – then processor can use information found in cache.

The term cache hit means the data or instruction processor need is in cache, cache miss – in the opposite situation.

There is three types of cache:

direct-mapped cache;

fully associative cache;

N-way-set-associative cache.

In a fully associative cache every memory location can be cached in any cache line. This memory type significantly decreases amount of cache-line misses, considered as complex type of cache memory implementation.

In direct-mapped cache cache memory location maps to a single cache line. It can be used once per address per amount of time. Performance of this cache memory type is lower than others.

In N-way-set-associative cache, the most

Explanation:

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