Computers and Technology, 05.05.2020 05:01 aubreymoore4553

Consider a program that can execute with no stalls and a CPI of 1 if the underlying processor can somehow magically service every load instruction with a 1-cycle L1 cache hit. In practice, 15% of all load instructions suffer from an L1 cache miss, 10% of all load instructions suffer from an L2 cache miss, and 2% of all load instructions suffer from an L3 cache miss (and are serviced by the memory system). An L1 cache miss stalls the processor for 8 cycles while the L2 is looked up. An L2 cache miss stalls the processor for 15 cycles while the L3 is looked up. An L3 cache miss stalls the processor for an additional 100 cycles while data is fetched from memory. What is the CPI for this program if 30% of the program's instructions are load instructions

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Consider a program that can execute with no stalls and a CPI of 1 if the underlying processor can so...

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