Part 2: a) Write VHDL code for a top module that invokes necessary components to display the four decimal digits on four seven-segment displays of a NEXYX 4 FPGA. The top module takes the 100 MHz FPGA clock, a reset signal, an enabler signal as the inputs. b) Makes necessary changes in a constraint file to implement your design on the FPGA and present only the uncommented parts of the constraint file in your exam script.

Allison and her group have completed the data entry for their spreadsheet project. they are in the process of formatting the data to make it easier to read and understand. the title is located in cell a5. the group has decided to merge cells a3: a7 to attempt to center the title over the data. after the merge, allison points out that it is not centered and looks bad. where would the title appear if allison unmerged the cells in an attempt to fix the title problem?