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Write a report that captures your approach to a 6-bit synchronous 2-pipeline parallel adder. It should include: a. New pipeline architecture of your design where bit 0, bit 1, and bit 2 are in one pipeline stage; bit 3, bit 4, and bit 5 are in one pipeline stage. So, there are 2 pipeline stages.
b. VHDL code and testbench of the 6-bit synchronous 2-pipeline parallel adder. Note: Complete the VHDL testbench and determine the minimum clock period to continue obtaining correct pipeline adder results.
c. Your functional verification.

The following test cases for your synchronous pipeline adder are required:
A10 = (7,62)
B10 = (30, 63)
You must test for all A+B cases with initial carry-in Co = 0 and 1, which means you should verify a total of 4 1 2 = 8 input and output values.
Note: All answers in the waveforms must be labeled to show correct answers. Annotate the inputs and outputs in hexadecimal values next to their binary equivalents in the simulation waveform. Include all waveform snapshots.

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Write a report that captures your approach to a 6-bit synchronous 2-pipeline parallel adder. It shou...
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