Computers and Technology, 22.07.2020 03:01 JadedylaneH6980
This lab assignment requires you to design a shift register using D flip-flops and examine the function of a specific shift register TTL part. Cascade 4 DFFs according to lecture notes.
Part A: Design a 4-bit synchronous left-shift register using D flip-flops. Your shift register should have an asynchronous parallel load, serial in, serial out, and parallel out bus. You may convert a flip-flop of another type into a D flip-flop, if needed. Note that your DFF has asynchronous clear (CLR) and preset (PR) for loading zero/one.
NOTE: FYI, you can (N)AND "clock" of each DFF with "asynchronous CLR/PR" to create synchronous CLR/PR. Do that for practice.
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