In this exercise, we examine how data dependences affect execution in the basic 5 - stage pipeline described in Section 4.5. Problems in this exercise refer to the following sequence of instructions: or r1,r2,r3
or r2,r1,r4
or r1,r1,r2
Also, assume the following cycle times for each of the options related to forwarding:
Without Forwarding With Full Forwarding With ALU-ALU Forwarding Only
250ps 290ps 300 ps
1. <4.5> Indicate dependences and their type.
2. <4.5> Assume there is no forwarding in this pipelined processor. Indicate hazards and add nop instructions to eliminate them.
3. <4.5> Assume there is full forwarding. Indicate hazards and add NOP instructions to eliminate them.
4. <4.5> What is the total execution time of this instruction sequence without forwarding and with full forwarding? What is the speedup achieved by adding full forwarding to a pipeline that had no forwarding?
5. <44.5> Add flop instructions to this code to eliminate hazards if there is ALU-ALU forwarding only (no forwarding from the MEM to the EX stage).
6. <44.5> What is the total execution time of this instruction sequence with only ALU-ALU forwarding? What is the speedup over a no-forwarding pipeline?