2- A bus-organized CPU has registers with 36 bits each, an ALU and a destination decoder. The control word is given below. output Clock Input R1 R2 PN SETA SRT. Toad MUX MUX A bles BELLE decoder +||+ SET. D Arit 11 logic (ALU) OPR Output SELA SELB SELD OPR i- Complete the missing bits of the control word if the number of registers is 60 and the number of operations is 30 SELECTA SELECTB SELECTD OPR ii- How many multiplexers in the A-B buses, and what is the size of each multiplexer? BUSA BUSB MUX inputs to output iii- If the data transfer from each register to MUXA=15 ns, MUXB=15 ns and ALU needs 35 ns to produce an output, what is the total time needed to output the result of an operation that needs data from registers? iv. How many inputs and outputs are there in the ALU for data? ALU inputs ALU outputs