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Suppose we have a byte addressable computer that has a 32-byte cache with 8 bytes per block. the memory address is 8 bits long. the system accesses memory addresses (in hex) in this exact order: 6e, b9, 17, e0, 4e, 4f, 50, 91, a8, ab, ad, 93, and 94. (a) assuming the cache is direct mapped, what memory addresses will be in cache block 2 after the last address has been accessed? (b) assuming the cache is direct mapped, what is the hit ratio for the entire memory reference sequence given, assuming the cache is initially empty? (c) assuming the cache is 2-way set associative with a lru replacement policy, what is the hit ratio?

What is used to analyze and summarize your data without graphical support

In deadlock avoidance using banker’s algorithm, what would be the consequence(s) of: (i) a process declaring its maximum need as maximum possible for each resource. in other words, if a resource a has 5 instances, then each process declares its maximum need as 5. (ii) a process declaring its minimum needs as maximum needs. for example, a process may need 2-5 instances of resource a. but it declares its maximum need as 2.