CprE 381 – Computer Organization and Assembly Level Programming Spring 2018Lab #2 [Note: This is a fairly lengthy lab in which you will learn some good VHDL design practices that will be helpful in your later projects. By ‘structural’ VHDL code, we mean code that has only basic logic gates implemented behaviorally as well as component instantiation. In contrast, ‘dataflow’ VHDL code uses concurrent assignment statements and allows for a greater amount of abstraction of the underlying logic structure. No ‘behavioral’ code (i. e. processes) is needed to complete this lab, beyond those that would drive signal values in the testbenches.]0) Prelab. Read the lab thoroughly. Read the Free Range VHDL Tutorial, pages 5-53. At the end of Chapter 3, answer questions 4b), 5a), and 6. 1) A One’s Complementer unit is a combinational functional unit that takes a single input and negates each individual bit. Provide your solution to this problem (VHDL code, simulation waveforms) in a folder called ‘P1/’.(a) Implement an N-bit one’s complimenter using structural VHDL, with the included inv. vhd NOT gate design as the basic building block. [It is highly recommended that you create an entity using a "generic" port for the N value, similar to what is done in included file generate_example. vhd and further described in section 9.2 of Free Range VHDL. You can greatly simplify your code with a "generate / for" block, which essentially acts as a macro expansion. A generate for loop as shown in generate_example. vhd is essentially specifying an array of and2 modules and hooking up the corresponding bits of a std_logic_vector. The combination of generic ports and generates allow you to structurally specify parameterized components that can be reused throughout your term project. Spend some time designing reusable components now and make your final project easier!](b) Create a second architecture for this unit that makes use of dataflow VHDL only. [Create this as a second file with a new entity name, to simplify the testing of both modules concurrently.](c) Create a single testbench design that uses structural VHDL to wrap both of these one’s complementers into a single entity with shared inputs (but different outputs). Use ModelSim to test that both designs give consistent results for the N=32 configuration. Include a waveform screenshot in your report PDF. [An example VHDL testbench is provided as tb_and2.vhd.]