Consider the following computation: float A[1024] [1024], B[1024] [1024], C[1024][1024]; for (i=0; i<1024; i++) for (j=0; j<1024; j++) C[i][j] 0.5*(A[i][j] +B[j][i]); = Consider a processor with a cache with capacity of 1 Mbytes (i. e., 1024 x 1024 bytes) and linesize of 64 bytes. Assume that each element occupies 4 bytes. For each part below, perform cache miss analysis for each array independently, without considering the actual interleaved accesses to the elements. (a) [10 pts) Compute the number of cache misses for A, B, C, assuming a direct- mapped cache.
(b) [10 pts] Compute the total number of cache misses for A, B, C, assuming a fully associative cache.
(c) [10 pts] Compute the total number of cache misses, assuming a 4-way set- associative cache.
(d) [10 pts] What is the minimum additional capacity that must be added (keeping total capacity as a perfect power of 2) to the above direct-mapped cache (linesize stays as 64 bytes) in order that the number of cache misses for B becomes equal to the number of cache misses for A?
(e) [10 pts] What is the minimum degree of associativity required (linesize = 64, total capacity is 1 Mbyte, and associativity is a power of 2) for the number of cache misses for B to equal the number of cache misses for A?