Computers and Technology, 10.12.2020 16:30 desscraft30

For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache Tag Index Offset
63–10 9–5 4–0

Required:
a. What is the cache block size (in words)?
b. How many blocks does the cache have?
c. What is the ratio between total bits required for such a cache implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are recorded.

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For a direct-mapped cache design with a 64-bit address, the following bits of the address are used t...

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