g Write a Verilog implementation of the design you created in part (a). Commit and push the implementation to your repository for homework 5. The requirements for the implementation are listed below. (a) The module name must be hw5_q1b. (b) There must be 4 input ports: four 4-bit inputs A, B, C, and D. (c) There must be a single output port: a single 5-bit output result for the computed function (d) You may use as many