Consider a multiple-issue design. Suppose you have two execution pipelines, each capable of beginning execution of one instruction per cycle, and enough fetch/decode bandwidth in the front end so that it will not stall your execution. Assume results can be immediately forwarded from one execution unit to another, or to itself. Further assume that the only reason an execution pipeline would stall is to observe a true data dependence. Now how many cycles does the loop require? Latencies beyond single cycle
Memory LD +4
Memory SD +1
Integer ADD, SUB +0
Branches +1
ADDD +1
MULTD +5
DIVD +12
1 Loop: LD F2, 0(Rx)
2 IO: DIVD F8, F2, F0
3 I1: MULTD F2, F6, F2
4 I2: LD F4, 0(Ry)
5 I3: ADDD F4, F0, F4
6 I4: ADDD F10, F8, F2
7 I5: ADDI Rx, Rx, #8
8 I6: ADDI Ry, Ry, #8
9 I7: SD F4, 0(Ry)
10 I8: SUB R20, R4, Rx
11 I9: BNZ R20, Loop