Assume that an in-order execution processor has a CPI of 1.2 excluding memory accesses. 30% of all instructions are load/store instructions that generate memory accesses for data. The L1 cache has a hit time of 1 cycle and a miss rate of 10%; and the L2 cache has a hit time of 12 cycles, a miss rate of 20%, and a miss penalty of 100 cycles. (1) What is the average memory access time