Consider a computer system with level-1 cache (CL1) and level-2 cache (CL2); where, CL1 access time is 3 cycles, CL2 access time is 14 cycles, and the main memory access time is 130 cycles. For 1000 data requests, there are 100 CL1 misses and 20 CL2 misses. Calculate the speedup (round to two decimal places) due to CL2. [Hints: Calculate EAT1, calculate EAT2, and then calculate Speedup = EAT1/EAT2.)

The three logical operators used to write compound conditions are "and," "or," and "not." a: true b: false

When creating a presentation in libre office impress, where does the editing of slides take place? a. the slides panel b. the center panel c. the tasks panel, under the masters pages tab d. the tasks panel, under the layouts tab

You need to design a circuit that implements the functions in the following table: s0 s1 function0 0 a + 10 1 a – b1 0 a + b1 1 a – 1s0 and s1 are 1-bit control inputs to select the function of the circuit. inputs a and b are 4-bitnumbers in 2s complement form. the output is also a 4-bit number in 2s complement form.you are allowed to use only one ttl 7483 4-bit adder to implement all the functions. but anynumber of other components (except the adder) can be used.hint: design a combinational logic circuit to modify the input b and the “carry input” of theadder depending on the control inputs s0 and s1.important: lab grade will depend on the working of the circuit & will be checked of by your labinstructor.1. is the output valid for the following input combinations: a. s0 = 0, s1 = 0, a = 7, b = 3? b. s0 = 0, s1 = 1, a = 7, b = 3? c. s0 = 1, s1 = 0, a = -4, b = -5? d. s0 = 1, s1 = 1, a = -8, b = 6? 2. what is the range of inputs (for both a and b) that will produce the valid output for all the functions?