Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding(or bypassing) hardware. Use a pipeline timing chart like that shown in the textbook Figure C.5.Assume that the branch is handled by predicting it as not taken and that the branch outcomesand targets are known (including the PC update) by the end of the decode stage. If all memoryreferences take 1 cycle, how many cycles does this loop take to execute? Justify your answer.

Write a grading program for a class with the following grading policies: a. there are two quizzes, each graded on the basis of 10 points. b. there is one midterm exam and one final exam, each graded on the basis of 100 points. c. the final exam counts for 50% of the grade, the midterm counts for 25%, and the two quizzes together count for a total of 25%. (do not forget to normalize the quiz scores. they should be converted to a percentage before they are averaged in.) any grade of 90 or more is an a, any grade of 80 or more (but less than 90) is a b, any grade of 70 or more (but less than 80) is a c, any grade of 60 or more (but less than 70) is a d, and any grade below 60 is an f. the program will read in the student’s scores and output the student’s record, which consists of two quiz and two exam scores as well as the student’s average numeric score for the entire course and final letter grade. define and use a structure for the student reco