Dynamic random access memory (dram) nearly all devices that include some form of computational capability (phones, tablets, gaming consoles, laptops, use a type of memory known as dynamic random access memory (dram). dram is where the "working set" of instructions and data for a processor is typically stored, and the ability to pack an ever increasing number of bits on to a dram chip at low cost has been critical to the continued growth in computational capability of our systems. for example, a single dram chip today can store > 8 billion bits and is sold for . s3-s5 at the most basic level and as shown below, every bit of information that a dram can store is associated with a capacitor. the amount of charge stored on that capacitor (and correspondingly, the voltage across the capacitor) sets whether a "" or a "o" is stored in that location single dram bit cell access switch съ vbit in any real capacitor, there is always a path for charge to "leak" off the capacitor and cause it to eventually discharge. in drams, the dominant path for this leakage to happen is through the access switch, which we will model as a leakage to ground. the figure below shows a model of this leakage cbi leak fun fact: this leakage is actually responsible for the "d" in "dram" - the memory is "dynamic" because after a cell is written by storing some charge onto its capacitor, if you leave the cell alone for too long, the value you wrote in will disappear because the charge on the capacitor leaked away let's now try to use some representative numbers to compute how long a dram cell can hold its value before the information leaks away. let cbit 28 ff (note that 1 ff 1x 10-15f) and the capacitor be initially charged to 1.2 v to store a "1." vbit must be > 0.9v in order for the circuits outside of the column to properly read the bit stored in the cell as a "." what is the maximum value of lleak that would allow the dram cell retain its value for > 1 ms?