Q1 direct mapped cache i 30 points suppose we have 16 bit byte-addresses and the clock frequency is 2ghz. we have the cache parameters as follows: cache size: 4kib block size: 1 word (4 bytes) cache hit time: 2 cycles cache miss penalty: 100 cycles direct mapped cache now suppose we access the following addresses, in order: 0x, 0x0004, 0x0008, 0x000c, 0x1000, 0x1004, 0x1008, 0x100c, 0x, 0x0004, 0x0008, 0x000c q1.1

answer:

okay

explanation:

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