Atypical slot machine is shown to the left. it is a game of chance is which the player initiates the spinning of three separate displays and tries to stop the display motion at a time when all three display images match. a slot machine inspired game will use two seven segment displays in place of the three displays in the example. each slots royale sa seven-segment display will show one of four custom designed symbols. status information about the game will be shown in a third seven segment display. when a button is pressed, the two displays showing the game symbols begin to change at different rates. the displays continue to change as long as the button remains depressed. when the button is released, the symbols stop changing. the objective of the game is to try to stop when both displays show the same symbol. • a "win" symbol is shown in the status display if the two displayed symbols match when the button is released. • a "lose" symbol is shown in the status display if the two displayed symbols do not match when the button is released. • while the button is depressed and the symbols are changing, a neutral symbol appears in the status display to indicate that the game is in progress. the game has four speeds: test, slow, medium, and fast. at test speed the symbols change so slowly that it is easy to win and easy to test the function of the circuit. as the speed increases, the game becomes more challenging. the speed is selected using two input switches to specify the four possible sneeds. 2. design the circuit to create codes, the code for the game status symbols. a. write a verilog module my_status_code with two single bit inputs pb1 and eq. eq is 1 when the two game symbols are the same, and pb1 is 1 when the pushbutton is depressed. the logic circuit output is the 4-bit codes value (see 1bii above). from the problem statement description of the "win", "lose", and "in progress" displays, design the logic to generate the 4-bit value. i. how should the two most significant bits of the special symbol code be set? ii. write the logic expressions for the two least significant bits of the special symbol code. b. write a verilog module for my_status_code using continuous assignment. c. write another version of the verilog module using a case statement in an always block. d. write a third version using if-else statements in an always block.