You are given designs of 3 caches for a 16-bit address machine: d1: direct-mapped cache. each cache line is 1 byte. 10-bit index, 6-bit tag. 1 cycle hit time. d2: 2-way set associative cache. each cache line is 1 word (4 bytes). 7-bit index, 7-bit tag. 2 cycle hit time. d3: fully associative cache with 256 cache lines. each cache line is 1 word. 14-bit tag. 5 cycle hit time. answer the following set of questions: a) what is the size of each cache? b) how much space does each cache need to store tags? c) which cache design has the most conflict misses? which has the least? d) the following information is given to you: hit rate for the 3 caches is 50%, 70% and 90% but did not tell you which hit rate corresponds to which cache, which cache would you guess corresponded to which hit rate? why?