Design a 4-bit multifunction register that has a 4-bit input i, a 4-bit output q, parallel load control input ld, shift right control shr and shift right by 2 control shr2. let shr have the highest priority, followed by shr2. parallel load ld should have the lowest priority. draw each of the following: (i) the architecture for the register, (ii) the flip flop/mux bank, (iii) the combinational logic required to translate the external controls to mux controls. (iii) the necessary truth tables.

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