Consider a cmos inverter fabricated in a 65-nm cmos process for which vdd =1v, vtn =−vtp =0.35 v, and μncox =2.5μpcox =470 μa/v2. in addition, qn and qp have l = 65nm and(w/l)n =1.5.

(a) find wp that results in vm =vdd/2. what is the silicon area utilized by the inverter in this case?
(b) for the matched case in(a), find the values of voh, vol, vih, vil, nml, and nmh.
(c) for the matched case in (a), find the output resistance of the inverter in each of its two states.