The W/L ratios of the two differential transistors in a nmos differential amplifier are mismatched by 2%, and a CMRR>80dB is required. If _m=0.18m _=100 _=0.2 _^′=5 /m And if the tail current ideal source is replaced by a nmos transistor, find the necessary L for the bias current source transistor. What is the transconductance percent mismatch?

1in2 processor chip can be modelled as an isothermal plane wall of silicon, isothermal on both sides. the power input to the bottom of the plane wall, or the processing power of the chip, often called the thermal design power (tdp), is 100w. assume the periphery is adiabatic. the silicon is 400 microns thick. the temperature at the junction, or in this case on the bottom of the isothermal plane wall, is 85°c. what is the top surface temperature, assuming that the only mode of heat transfer is conduction