Introduction:
In this design problem, you will have the opportunity to draw together all of the concepts and skills that you have developed pertaining to the topic of synchronous counter design. You will design, simulate, and create a Sixty Second Timer.

Equipment:
Circuit Design Software (CDS)
Digital MiniSystem (DMS)
-myDAQ
-myDigital Protoboard
-Cmod S6 FPGA Module
-#22 Gauge solid wire

Procedure:
Design (60 Second Timer)
Design a digital Sixty Second Timer that counts from 00 to 59. This design has two control inputs and two output displays. The two inputs are Clock and Reset. The Clock signal is a 1 Hz square wave that controls the count rate. The Reset signal, when it is a logic zero, resets and holds the count at zero. When the Reset signal is a logic one, counting is enabled. When the count reaches sixty seconds, the counting resets at zero.

Design Specifications:
The two output displays are common cathode seven-segment displays that will require a multiplexed signal.
Each display will use a 74LS48 BCD-To-Seven-Segment display driver in Design Mode. (DEC_BCD_7 in PLD Mode)
The ones-unit display (0-9) is controlled by a synchronous counter designed with a 74LS163 MSI counter IC. (CNTR_4BIN_S in PLD Mode)
The tens-unit display (0-6) is controlled by a synchronous counter designed with SSI logic gates (J/K).
Any additional logic may be used as needed to support the counter designs.
Simulation (Design Mode or PLD Mode)
Using the Circuit Design Software (CDS) enter and test your Sixty Second Timer design.
Design Mode Option:
If you choose to create the circuit in Design Mode to simulate, remember that you will need to re-create the circuit in PLD Mode to prototype the circuit.
PLD Mode Option:
You can bypass the need to re-create the circuit a second time by creating and simulating the circuit in PLD Mode. Just remember that you will not have an SSD for simulation in PLD Mode. You will need to use probes to track the counts and events.