Consider the design of a CMOS gate computing F = � ∙ � ∙ � ∙ � a) Sketch a transistor-level schematic for this gate. (5 points) b) Annotate the sketch with transistor widths chosen to achieve effective rise and fall resistance equal to a unit (2/1) inverter. (5 points) c) Estimate the rise and fall propagation delays in terms of R and C of this gate driving h identical gates. Explain the relative transition times and values of the inputs to achieve these delays. (10 points) d) Estimate the best-case (contamination) delays of the gate. Explain the relative transition times and values of the inputs to achieve these delays. (10 points)