Consider two designs for the 5-stage pipelined architecture. In the first design, the branch condition and target are resolved in the MEM stage, while in the second design, the branch condition and target are resolved in the ID stage, but the clock cycle time is 10% larger than in the first design. Assuming that I. the instruction mix executing on the pipeline contains 25% branch instructions, 70% of which are taken. II. the CPI of both designs is 1.5 if we do not account for stalling due to control hazards. a. Compute the CPI for each of the two designs when the effect of control hazards is accounted for. b. Specify which of the two designs would be more efficient.