URGENT Help with a JK/D Flip Flops, any help would be immensely appreciated.

Anything that you can do will be better than nothing, submit even if it's not complete, Thank You.

Design a counter with an external control, x, to count the sequence of multiples of 3 (i. e., 0-3-6 and repeat) when the control is 0, and non-multiples of 3 (i. e., 1-2-4-5-7 and
repeat) when the control is 1. These values will be displayed on a seven-segment display.

When the control value changes, the first clock should drive the output to the first value in the appropriate count- e. g., if the circuit has been counting
non multiples and the control switches to 0, the first clock should drive the output to 0 (or if you have been counting multiples and the control switches to 1, the first clock pulse
should make the output.

1). Use JK or D flip-flops. For input and output circuits, you may use any chips available in the lab but you must justify your choice, both of your design and of the flip flops you use (combinational logic, decoder, or PLD).

You must demonstrate your counter using your 7-segment display and any additional logic gates/devices that you need to control the circuit.

Note that in a circuit using edge-triggered flip-flops, it may be necessary to use a debounced switch as the clock. Find a suitable circuit that can be built with the items
available in our lab (either online or in a text), and include it, and a proper reference for it, with your prelab.

The prelab you turn in in the lab must include the 1)state table and 2)state diagram for your design, 3)Karnaugh maps (or whatever documentation is required to support your
design) and a 4)schematic of your circuit, (with all pins and gates labeled), along with the debounced switch you found, and the reference to it. NOTE: the debounced switch
design must be done before you come to the lab.