1. Write a Verilog declaration of the following wires: a. A32-bit wire having name data_bus and type wire
b. Scalar wires clock, set, and reset.2.

2. Write a Verilog declaration of the following registers:

a. A 32-bit register having name operand_I and type reg.
b. An integer having name K.
c. A 32 × 64 two-dimensional array of 16-bit words having name Pixel_Color.

3. What characters does Verilog allow in an identifier?

a. Verilog is case sensitive.
b. Built-in primitives describe only combinational logic.
c. The right arithmetic shift operator is denoted by >>.
d. The output po