Write a Verilog module that describes 8-bit right shifter register with control signals A(arithmetic), L(logical), CLR(clear) and LD(load). Input signals are CLK, LD and 8-bit input D. Output signal is 8-bit output Q. CLR signal will clear Q. LD signal will load input D to Q. A signal will do arithmetic right shift of Q, while L signal will do logical right shift of Q.

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in baseband transmission the whole bandwidth of the cable is utilized by a single signal. eg.Ethernet is using Basebands for LAN.

In the broadband transmission, multiple signals are sent on multiple frequencies simultaneously using a single channel. eg.Digital Subscriber Line (DSL)