A J-K flip-flop is being used as a divide-by-2 circuit when . Group of answer choices the J and K inputs are tied to ground the J and K inputs are tied to Vcc the reset is tied to the clock all the inputs are connected to the preset

the J and K inputs are tied to Vcc.

Explanation:

A J-K flip-flop can be defined as a gated set-reset (SR) flip-flop with an additional clock input circuit that is being used as a feedback to prevent any invalid or illegal output condition that may arise, when the set (S) and reset (R) inputs are equal to logic level 1.

Basically, in a set-reset (SR) flip-flop the set (S) should have a logic level output that is equal to 1 while the reset (R) has 0; these two levels as the name implies, are used to set and reset the device respectively.

A J-K flip-flop is being used as a divide-by-2 circuit when the J and K inputs are tied to Vcc i.e the ground voltage. Thus, the set and reset pins are not being used but are rather tied to Vcc in a divide-by-2 circuit.

answer:

you cant but you can report the sender

and do you want to talk?

im xavier btw but i go by x

explanation: