Suppose you want to build a digital logic project using only NAND gates. The output of each NAND gate will be connected to the inputs of one or more other NAND gates. Assume that the logic chips you are using have the following characteristics. Compute the DC noise margin and the largest fanout (number of gate inputs connected to a single output) that you can achieve while still maintaining the stated DC noise margin. VCC= 4.5V VOH= 4.0 V VOL= 0.5V VIH= 2.4V VIL=2.1V
VTH= (VOH- VOL)/2 IOH= -10μA IOL= 10μA IIH= 1μA IIL= -1μA

Calculate the following values:
a. Noise margin for HIGH (Volts):
b. Noise margin for LOW (Volts):
c. Noise margin overall (Volts):
d. Practical Fanout for HIGH:
e. Practical Fanout for LOW:
f. Practical Fanout overall:

a) 1.6 V

b) 1.6 V

c) 1.6 v

d) 10

e) 10

f) 10

Explanation:

Calculate the following

A) Noise margin for HIGH ( volts )

 = Voh - Vih

 =  4 - 2.04 = 1.6 V

B) Noise margin for LOW ( volts )

 = Vil - Vol

 = 2.1 - 0.5 = 1.6 V

C) Noise margin overall ( volts )

 = min { NMi , NMl }

 = 1.6 v

D ) practical Fanout for HIGH

 FOH =

attached below is the remaining part of the solutions

answer:

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