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Engineering, 06.05.2021 04:40 unknown9263

The fin array of Problem 3 142 is commonly found in compact heat exchangers, whose function is to provide a large surface area per unit volume in transferring heat from one fluid to another. Consider conditions foe which the second fluid maintains equivalent temperatures at the parallel plates, thereby establishing symmetry about the midplane of the fin array. The heat exchanger is 1 m long in the direction of the flow of air (first fluid) and 1 m wide in a direction normal to both the airflow and the fin surfaces. The length of the fin passages between adjoining parallel plates is L = 8 mm. whereas the fin thermal conductivity and convection coefficient are k = 200W/m middot K (aluminum) and h = 150W/m^2 middot K, respectively. If the fin thickness and pitch are t = 1 mm and S = 4 mm. respectively, what is the value of the thermal resistance for a one-half section of the fin array? Subject to the constraints that the fin thickness and pitch may not be less than 0.5 and 3 mm, respectively, assess the effect of changes in t and S. An isothermal silicon chip of width W = 20 mm on a side is soldered to an aluminum heat sink (k = 180 W/m middot K)of equivalent width. The heat sink his a have thickness of L_b = 3 mm and an array of rectangular fins, each of length L_f = 15 nun Airflow at 20 degree C is maintained through channels formed b> Use fins and a cover plate, and for a convection coefficient of h = 100 W/m^2 middot K, a minimum fin spacing of 1.8 mm is dictated by limitations on the flow pressure drop. The solder joint has a thermal resistance of 2 times 10^-6 m^2 middot K/W. Consider limitations for which the array has N = 11 fins, in which case values of the fin thickness t = 0.182 mm and pitch S = 1.982 mm are obtained front the requirement that W = (N - 1)S + r and S - t = 1.8 mm. If the maximum allowable dap temperature is T_c = 85 degree C, what is the corresponding value of the chip powers? An adiabatic fin tip condition may he assumed, and airflow along the surfaces of the heat sink may be assumed to provide a convection coefficient equivalent to that with airflow through the channels. With (S - t) and h fixed at I .8 mm and 100 W/m^2 middot K, respectively, explore the effect of increasing the fin thickness by reducing the number of fins. With N = 11 and S - t fixed at 1.8 mm, but relaxation of the constrain on the pressure drop, explore the effect of increasing the airflow, and hence the convection coefficient. As seen in Problem 3.109, silicon carbide nanowires of diameter D = 15 run can be grown onto a solid silicon carbide surface by carefully depositing droplets of catalyst liquid onto a flat silicon carbide substrate. Silicon carbide nanowires grow upward from the deposited drops, and it the drops are deposited lira pattern, an array of nanowire fins can be grown, forming a silicon carbide nano-heat sink. Consider tinned and unfinned electronics packages in which an extremely small, 10 mu m times 10 mu m electronics device it sandwiched between two d = 100-nm-ttuck silicon carbide them in both cases, the coolant is a dielectric liquid at 20 degree C. A heat transfer coefficient of h = 1 times 10^5 W/m^2 middot K exists on the top and bottom of the unfinned package and on all surfaces of the exposed silicon carbide fins, which are each L = 300 nm tong. Each nano-heat sink includes a 200 times 200 array of nanofins. Determine the maximum allowable heat rate that can he generated by the electronic device to that its temperature is maintained at T_1 < 85 degree C for the unfinned and finned packages.

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